FM25B • 7
cuit tells the user when their transmitter has locked on frequency and when an
applied audio signal is being transmitted. U1:A takes the PLL correction
pulses and amplifies them. The feedback resistor network formed by R6 and
R8 set the gain of the amplifier (remember that classic formula ‘G=1+Rf/Ri’ =
1+1 MegΩ / 10KΩ). The output of U1:A is then rectified by D2 and the peak
voltage is stored by C2. R2 is used as a discharge ‘Bleeder’ resistor so that
the sampled peak-hold voltage on C2 will vary up and down fast enough to
give the reliable dual indication features we need. U1:B monitors the peak
voltage stored on C2 and turns on or off the D1 LED Frequency Lock / Audio
Modulation indicator. When a large number of correction pulses are present
on the PLL output, due to the user changing frequency or the unit become
unlocked, the resulting voltage on C2 will be high enough on the inverting in-
put of U1:B to swing the output Low. When the output of U1:B is low, the LED
(D1) is turned off indicating that the unit is unlocked. The similar scenario ap-
plies when audio is being transmitted. The audio being transmitted varies the
frequency up and down (FM – Frequency Modulation) in accordance with the
music. The PLL tries to correct for these deviations from the center transmis-
sion frequency by sending out short pulses. The positive feedback provided by
R9 adds a bit of hysteresis to U1:B’s response by changing the crossover trig-
ger point switching the output back and forth from High to Low. The resulting
effect is to smooth the response of the LED (D1) indicator making it more
pleasant to the eye. The detection circuit formed by U1 will indicate when au-
dio is being transmitted by flashing D1 along with the music. Not bad…two for
the price of one!
U2 acts as the brains of the whole circuit. This microcontroller looks at the set-
tings of each of the dip switches S1 through S3 one at a time and from these it
calculates the desired frequency. The switches allow you add up the closed
(down) positions 1, 2, 4, and 8 to make any number between 0 and 9. For ex-
ample closing position 1 and 8 on S3 (10 MHz switch) is equal to 90 MHz.
Closing 1 and 4 on S2 (1 MHz switch) is equal to 5 MHz. Closing 2 and 1 on
S1 (0.1 MHz switch) is equal to 0.3 MHz. This makes the final frequency equal
to 95.3 MHz. These switches may be set to any frequency between 88 and
108 MHz. To set the frequency above 100 MHz, the S3 positions must add up
to ten. Any switch setting greater than 9, with the exception of S3, is invalid
and will be read as 0.
Once this frequency is determined, the information needed to control U3 is
sent serially from U2. This information is a string of binary data, (1's and 0's).
In this way data is sent one bit at a time to U3. The frequency information
takes 10 bits of data along with an additional 6 bits sent for the internal control
and transmission mode (stereo / mono) selection. You may think that all this
would take a long time but in fact the whole process of sending the data takes
less than 1/100th of a second!
U3’s internal phase locked loop (PLL) synthesizer requires a 7.6 MHz refer-
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